AMD Geode SC1201 Bedienungsanleitung Seite 314
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314 AMD Geode™ SC1200/SC1201 Processor Data Book
Video Processor Module
32579B
Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field
Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field
Vertical Retrace - Logical Lines 4-9 — Scan Lines 4-9
Vertical Retrace - Logical Lines 10-21 — Scan lines 10-21
Vertical Retrace - Logical Lines 22, 23 — Scan lines 22, 23
Active Video
Logical Line 24 — Scan Lines 24-263
Vertical Retrace - Logical Line 24 — Scan Line 1
Vertical Retrace - Logical Lines 2, 3 — Scan Lines 2, 3
VSYNC Start
VBI_Total_Count_Odd
VBI_Line_Offset_Odd
(Not normally User Data)
(Nominal VBI Lines)
(Not normally User Data)
(Not normally User Data)
VSYNC End
Vertical Retrace - Logical Lines 4-9 — Scan Lines 267-272
Nominal VBI Lines 10-21 — Scan lines 273-284
Vertical Retrace - Logical Lines 22,23 — Scan lines 285, 286
(Not normally User Data)
Active Video
Logical Line 24 — Scan Lines 287-525
Vertical Retrace - Logical Line 24 — Scan Line 264
Vertical Retrace - Logical Lines 2, 3 — Scan Lines 265, 266
(Not normally User Data)
VSYNC End
VBI_Total_Count_Even
VBI_Line_Offset_Even
(Not normally User Data)
(Nominal VBI Lines)
VSYNC Start
- AMD Geode™ SC1200/SC1201 1
- Processor Data Book 1
- Contents 3
- List of Figures 5
- List of Tables 10
- 1.0Overview 13
- 1.2 Features 14
- Overview 16
- 2.0Architecture Overview 17
- 2.2 Video Processor Module 22
- 2.3 Core Logic Module 22
- 2.4 SuperI/O Module 23
- Architecture Overview 24
- 3.0Signal Definitions 25
- Signal Definitions 26
- 3.1 Ball Assignments 27
- AMD Geode™ 28
- SC1200/SC1201 28
- Processor 28
- 3.2 Strap Options 44
- 3.4 Signal Descriptions 49
- 3.4.5 TV Interface Signals 54
- 3.4.10 IDE Interface Signals 61
- 3.4.17 GPIO Interface Signals 67
- Reserved - RSVD 78
- 4.3 WATCHDOG 79
- 4.3.2 WATCHDOG Registers 80
- 4.4 High-Resolution Timer 81
- 4.5 Clock Generators and PLLs 83
- Circuitry 84
- 4.5.2 GX1 Module Core Clock 85
- 4.5.3 Internal Fast-PCI Clock 85
- 4.5.4 SuperI/O Clocks 86
- 4.5.6 Video Processor Clocks 86
- 4.5.7 Clock Registers 87
- 5.0SuperI/O Module 89
- 5.1 Features 90
- 5.2 Module Architecture 91
- 5.3.4 Address Decoding 93
- SuperI/O Module 100
- 5.5 Real-Time Clock (RTC) 105
- 5.5.3 RTC Registers 111
- Table 5-19. RTC Register Map 111
- Table 5-20. RTC Registers 111
- Table 5-25. Extended RAM Map 115
- Table 5-24. Standard RAM Map 115
- 5.6.1 Event Detection 116
- 5.6.2 SWC Registers 117
- 5.7 ACCESS.bus Interface 121
- 5.7.3 Acknowledge (ACK) Cycle 122
- 5.7.6 Arbitration on the Bus 123
- 5.7.7 Master Mode 123
- 5.7.8 Slave Mode 125
- 5.7.9 Configuration 125
- 5.7.10 ACB Registers 126
- Table 5-31. ACB Register Map 126
- Table 5-32. ACB Registers 126
- 5.8 Legacy Functional Blocks 129
- Offset Name 130
- 404h EDR Data Bits 130
- Architecture 131
- Table 5-42. Bank 0 Bit Map 133
- Table 5-43. Bank 1 Bit Map 133
- Table 5-44. Bank 2 Bit Map 134
- Table 5-45. Bank 3 Bit Map 134
- Port 3 (SP3) Functionality 135
- Table 5-55. Bank 0 Bit Map 138
- Table 5-56. Bank 1 Bit Map 139
- Table 5-57. Bank 2 Bit Map 139
- Table 5-58. Bank 3 Bit Map 139
- Table 5-59. Bank 4 Bit Map 139
- Table 5-60. Bank 5 Bit Map 140
- Table 5-61. Bank 6 Bit Map 140
- Table 5-62. Bank 7 Bit Map 140
- 6.0Core Logic Module 141
- 6.2 Module Architecture 142
- 6.2.2 PSERIAL Interface 143
- 6.2.3 IDE Controller 144
- Core Logic Module 146
- 6.2.4 Universal Serial Bus 147
- 6.2.5 Sub-ISA Bus Interface 147
- 6.2.6 AT Compatibility Logic 152
- Figure 6-7. PIT Timer 154
- 6.2.8 Keyboard Support 157
- 6.2.9 Power Management Logic 158
- Sleep States 160
- 6.2.11 GPIO Interface 167
- 6.2.12 Integrated Audio 167
- SMI# (System Management 171
- Read to Clear 172
- Figure 6-15. Typical Setup 173
- Table 6-12. Cycle Types 174
- 6.3 Register Descriptions 175
- 6.3.2 Register Summary 176
- GPIO and LPC Support Summary 176
- 6.4 Chipset Register Space 190
- CPI mode 202
- — SDATA_IN2 210
- — IRRX1 (CEIR) 210
- 1), this bit allows signal 231
- ]. Reading 241
- 15:6 Reserved 241
- Not Used Reset Value: 00h 246
- 0 Reserved. (Read Only) 262
- Not Used 271
- Reserved Reset Value = xxh 294
- 7.0Video Processor Module 311
- 7.1 Module Architecture 312
- 7.2 Functional Description 313
- Active Video 314
- 7.2.1 Video Input Port (VIP) 315
- Figure 7-4. VIP Block Diagram 315
- Video Processor Module 316
- 7.2.2 Video Block 320
- 7.2.3 Mixer/Blender Block 323
- [13, 11:9] 324
- Mixing/Blending Operation 327
- 7.2.4 TVOUT Block 329
- 7.2.6 Integrated DACs 330
- 7.2.7 TFT Interface 331
- 7.2.8 Integrated PLL 332
- 7.3 Register Descriptions 333
- 29:20 Reserved 355
- 8.0Debugging and Monitoring 363
- Debugging and Monitoring 364
- 9.0Electrical Specifications 365
- 9.1.4 Operating Conditions 366
- 9.1.5 DC Current 367
- Electrical Specifications 368
- 9.2 DC Characteristics 371
- 9.3 AC Characteristics 376
- 9.3.3 CRT and TFT Interface 382
- 9.3.4 TV Interface 384
- 9.3.5 ACCESS.bus Interface 385
- Ω1 KΩ 10 pF 388
- Figure 9-19. PCI Reset Timing 393
- 9.3.7 Sub-ISA Interface 394
- 9.3.8 LPC Interface 398
- Table 9-25. LPC and SERIRQ 398
- 9.3.9 IDE Interface Timing 399
- 9.3.12 Fast IR Port Timing 422
- 9.3.13 Parallel Port Timing 423
- 9.3.15 Power Management 432
- 9.3.16 Power-Up Sequencing 433
- 9.3.17 JTAG Interface 435
- 10.0Package Specifications 437
- Figure 10-1. Heatsink Example 438
- 10.2 Physical Dimensions 439
- Package Specifications 440
- A.1 Order Information 441
- Table A-1. Revision History 442
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