AMD Duron Bedienungsanleitung Seite 14

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2 Overview Chapter 1
AMD Duron Processor Data Sheet 23802ESeptember 2000
Preliminary Information
AMD system bus. The AMD system bus combines the latest
technological advances, such as point-to-point topology,
source-synchronous packet-based transfers, and low-voltage
signaling, to provide the most powerful, scalable bus available
for any x86 processor.
The AMD Duron processor is binary-compatible with existing
x86 software and backwards compatible with applications
optimized for MMX and 3DNow! instructions. Using a data
format and single-instruction multiple-data (SIMD) operations
based on the MMX instruction model, the AMD Duron
processor can produce as many as four, 32-bit, single-precision
floating-point results per clock cycle. The enhanced 3DNow!
technology implemented in the AMD Duron processor includes
new integer multimedia instructions and software-directed
data movement instructions to deliver a superior performance
to Celeron in multimedia and number-intensive applications.
1.1 AMD Duron Processor Microarchitecture Summary
The following features summarize the AMD Duron processor
microarchitecture:
The industrys first nine-issue, superpipelined, superscalar
x86 processor microarchitecture designed for high clock
frequencies
Multiple x86 instruction decoders
Three out-of-order, superscalar, fully pipelined
floating-point execution units, which execute all x87
(floating-point), MMX and 3DNow! instructions
Three out-of-order, superscalar, pipelined integer units
Three out-of-order, superscalar, pipelined address
calculation units
72-entry instruction control unit
Advanced dynamic branch prediction
Enhanced 3DNow! technology with new instructions to
enable improved integer math calculations for speech or
video encoding and improved data movement for internet
plug-ins and other streaming applications
200-MHz AMD system bus (scalable beyond 400 MHz)
enabling leading-edge system bandwidth for data
movement-intensive applications
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