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Chapter 6 Electrical Data 23

23802E—September 2000 AMD Duron™ Processor Data Sheet

Preliminary Information

Figure 8. SYSCLK and SYSCLK# Differential Clock Signals

Table 11 shows the SYSCLK/SYSCLK# differential clock AC

characteristics. Figure 9 shows a sample waveform.

Table 10. SYSCLK and SYSCLK# DC Characteristics

Symbol Description Min Max Units

Threshold-DC

Crossing before transition is detected (DC) 400 mV

Threshold-AC

Crossing before transition is detected (AC) 450 mV

LEAK_P

Leakage current through P-channel pullup to VCC_CORE —1mA

LEAK_N

Leakage current through N-channel pulldown to VSS (Ground) 1 mA

CROSS

Differential signal crossover

VCC_CORE/2

+/– 100

Capacitance 4 12 pF

CROSS

Threshold-DC

= 400mV V

Threshold-AC

= 450mV

Table 11. SYSCLK and SYSCLK# AC Characteristics

Symbol Description Min Max Units Notes

Clock Frequency 50 100 MHz

Duty Cycle 30% 70% –

Period 10 ns 1, 2

High Time 4 ns

Notes:

1. Circuitry driving the SYSCLK and SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track

the jitter. The –20 dB attenuation point, as measured into a 10-pF or 20-pF load must be less than 500 kHz.

2. Circuitry driving the SYSCLK and SYSCLK# inputs may purposely alter the SYSCLK and SYSCLK# period (spread spectrum clock

generators). In no cases can the period violate the minimum specification above. SYSCLK and SYSCLK# inputs may vary from

100% of the specified period to 99% of the specified period at a maximum rate of 100 kHz.

3. Measured from 0.5 V to VCC_CORE

4. Measured from VCC_CORE to 0.5 V

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AMD Duron Bedienungsanleitung Seite 35