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60 Pin Descriptions Chapter 9

AMD Duron™ Processor Data Sheet 23802E—September 2000

Preliminary Information

that allows PGA key pins only where permitted. However,

sockets that populate all key pins must be allowed, so the

motherboard must always provide for pins at all key pin

locations.

NC Pins The motherboard should provide a plated hole for an NC pin.

The pin hole should not be electrically connected to anything.

NMI Pin NMI is an input from the system that causes a non-maskable

interrupt.

PGA Orientation Pins No pin is present at pin locations A1 and AN1 (see the Processor

Socket 462 Application Note, order# 90020). Motherboard

designers should not allow for a PGA socket pin at these

locations.

PLL Bypass and Test

Pins

PLLTEST# (AC3), PLLBYPASS# (AJ25), PLLMON1 (AN13),

PLLMON2 (AL13), PLLBYPASSCLK (AN15), and

PLLBYPASSCLK# (AL15) are the PLL bypass and test

interface. This interface is tied disabled on the motherboard.

All six pin signals are routed to the debug connector. All four

processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and

PLLMON2) are tied to VCC_CORE with 1-kohm resistors.

PWROK Pin Motherboard designs require power sequencing circuitry for

processor PLL startup protection. PLL startup complications

can occur if PWROK is asserted before the following voltages

are valid:

■ VCC_CORE

■ PLL voltage

■ 3.3-V supply, which indicates the system clocks are stable.

For more information, see the PWROK Signal Motherboard

Design Application Note, order# 90024 and the “Motherboard

Required Circuits” chapter of the Motherboard PGA Design

Guide, order# 90009.

SADDIN[1]# and

SADDOUT[1:0]# Pins

SADDIN[1]# is tied to VSS with 1-kohm resistors, if this bit is

not supported by the Northbridge. SADDOUT[1:0]# are NC, if

these bits are not supported by the Northbridge. For more

information, see the AMD System Bus Specification, order#

21902.

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