
List of Figures vii
23802E—September 2000 AMD Duron™ Processor Data Sheet
Preliminary Information
List of Figures
Figure 1. Typical AMD Duron™ Processor System Block Diagram . . . . . 3
Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. AMD Duron Processor Power Management States. . . . . . . . . . . 9
Figure 4. Example System Bus Disconnection Sequence . . . . . . . . . . . . . 13
Figure 5. Exiting Stop Grant State/Bus Reconnection Sequence . . . . . . 14
Figure 6. System Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Processor Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 23
Figure 9. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Signal Relationship Requirements during Power-Up
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Typical SIP Protocol Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12. PGA Package, Top, Side, and Bottom Views . . . . . . . . . . . . . . . 38
Figure 13. Socket A with Outline of Socket and Heatsink Tab . . . . . . . . . 39
Figure 14. Socket A Heatsink Tab Side View . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15. AMD Duron Processor Pin Diagram—Topside View . . . . . . . . 42
Figure 16. PGA OPN Example for the AMD Duron Processor. . . . . . . . . . 65
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