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18522F/0—Jan1997 AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
results, recover from mispredictions and exceptions, and hold
the relative speculative state.
The processor’s 16-entry reorder buffer stores results from x86
instructions that have been speculatively executed at the time
a branch was predicted. When ROPs are dispatched to one of
the processor’s six independent execution units, an entry at
the top of the reorder buffer is allocated for each ROP. Up to
four entries are allocated simultaneously. The reorder buffer
keeps track of the original instruction sequence and ensures
that results are retired in program order, writing the results of
the executed instruction to the register file. If a branch is
mispredicted, the results of the instructions along the mispre-
dicted path are invalidated in the reorder buffer before there
is any effect on the x86 registers or memory system.
4.10 Register File
A problem with the x86 architecture has been its limited num-
ber of general-purpose registers. Fewer registers means fre-
quent reuse of registers, which potentially leads to a reduction
in performance. The AMD-K5 CPU utilizes register renaming
and avoids this performance reduction.
Because the movement of values between registers and mem-
ory locations is unavoidable with the x86 instruction set, a key
advantage of the AMD-K5 CPU is its single-cycle load from the
data cache. This, in combination with the multiported register
file and renaming in the reorder buffer, gives near optimal
speculative performance within the constraints of the x86
instruction set.
4.11 The Right Combination—Compatibility and Performance
While each feature has a significant function, it is the combina-
tion of all features that is responsible for the AMD-K5 proces-
sor’s overall design and performance advantages.
Compatibility with the Microsoft Windows operating system
and the immense library of x86 software furthers these advan-
tages, and is the foundation of the AMD-K5 processor’s lead-
ing-edge solution.
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