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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

PCD Page Cache Disable Output

The PCD signal provides cacheability status by reporting the

contents of the PCD bit in CR3, the page directory, or the page

table entry. PCD reflects the state of the PCD bit in CR3 if

non-paged cycles occur. In Real mode or Protected mode when

paging is disabled, PCD reflects the state of the CD bit in CR0.

PCHK Parity Status Output

The PCHK signal is asserted to indicate a data parity error for

data read cycles. It may be sampled for parity status on the sec-

ond clock after BRDY is sampled as asserted. Except during

Test mode, PCHK is never floated.

PEN Parity Enable Input

PEN, when asserted on a parity error, causes the address and

control signals of the cycle to be latched into the machine

check registers. The MCE bit in CR4, if set, will cause a vector

to the machine check exception before another instruction is

executed.

PRDY Probe Ready Output

The processor asserts PRDY to acknowledge the system logic’s

assertion of R/S or execution of the Test Access Port (TAP)

instruction, USEHDT, and to indicate the processor’s entry

into the Hardware Debug Tool (HDT) mode for debugging.

PWT Page Write-Through Output

The PWT signal provides writeback status by reporting the

contents of the PWT bit in CR3, the page directory, or the page

table entry. The PWT signal reflects the state of the PWT bit in

CR3 when non-paged cycles occur or paging is disabled. In

Real mode or Protected mode, when paging is disabled, PWT

will be zero.

RESET Reset Input

The processor will reset when the RESET signal is asserted.

The processor cannot begin execution until at least 1 ms after

, BF, and CLK have stabilized. The operating mode is

determined by the state of the FLUSH, INIT, and FRCMC sig-

nals during the falling edge of RESET. (See FLUSH, INIT,

FRCMC, and Switching Characteristics t

and t

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AMD K5 Bedienungsanleitung Seite 32