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18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

■ Adds the EWBE input to indicate an empty external write

buffer (This supports strong store ordering between the

processor and the external memory system. All writes to

exclusive/modified lines are held until EWBE is asserted to

indicate that no writes are pending in the external memory

system.)

■ On read-modify-write cycles, guarantees an idle cycle

between consecutive locked accesses

■ Implements non-cacheable code prefetches as eight bytes

instead of 16 bytes (Each is treated as a single 8-byte access

when non-cacheable.)

■ Supports JTAG pins TCK, TDI, TDO, TMS, and TRST

■ Supports external breakpoints with the pins BP3–BP0

■ Requires some writebacks and line fills to be run as burst

cycles (With no BLAST pin, burst writebacks cannot be ter-

minated in the middle of the burst.)

■ Drives burst length information with the CACHE pin (This

pin always indicates a fixed burst length of four 64-bit

accesses. The corresponding pin is BLAST on the Am486

processor—where the burst is typically four 32-bit

transfers—but can be longer with narrower width memo-

ries.)

■ Supports simple Master/Slave modes through the pins

FRCMC and IERR

■ Aborts a cycle if BOFF is asserted in the middle of the cycle

(When BOFF is negated, the cycle restarts from the begin-

ning. The Am486 processor restarts the cycle at the point it

was aborted.)

8.9 P54C and AMD-K5 Processor Bus Differences

The AMD-K5 processor has two possible drive strengths, weak

and strong. These strengths are equivalent to weak and strong

on the Pentium processor. The recommended, default drive

strength on the AMD-K5 processor is weak.

For detailed difference information, refer to Appendix A of

the AMD-K5 Processor Technical Reference Manual, order#

18524, or the AMD-K5 Processor Application Note, “Compari-

son of the AMD-K5, Pentium, and 486 Processors,” order#

20025.

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AMD K5 Bedienungsanleitung Seite 65