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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

the external memory system is ready to receive data adds addi-

tional wait states, if they are needed. The processor ceases

driving the current data element upon receiving the BRDY sig-

nal. (See Figure 33 on page 76.)

Figure 6. Burst Write (One Wait State)

The external signal KEN is ignored for burst write cycles since

these are previously cached lines. Writebacks can occur as a

result of the following:

■ Replacement of a data cache entry that is modified

■ An inquire cycle that hits in a modified line

■ Assertion of the WBINVD instruction

■ Assertion of the external signal FLUSH

Only one line is sent for inquire or replacement accesses.

Assertion of FLUSH or execution of WBINVD results in the

modified lines in the entire cache being written back as a

series of single line writes. An inquire or replacement access

results in a writeback of only one line.

BOFF or AHOLD/

HOLD/HLDA During

Burst Transfers

BOFF or AHOLD can be asserted during a burst transfer. The

processor will abort a cycle if BOFF is asserted in the middle of

the cycle. When BOFF is negated, the cycle is restarted from

the beginning.

If AHOLD is asserted, the processor responds by floating the

address pins in the next clock cycle. The system can then drive

the address and assert EADS to generate an inquire cycle

CLK

ADS

BRDY

W/R

CACHE

Data

Add/

Control

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AMD K5 Bedienungsanleitung Seite 50