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AMD-K5 Processor Data Sheet 18522F/0—Jan1997
PRELIMINARY INFORMATION
Pipelining is not supported for the following cycles:
■ Non-cacheable instruction cache cycle into a non-cacheable
instruction cache cycle
■ Non-cacheable instruction cache cycle into a write cycle
(could be I/O)
■ Cacheable instruction cache cycle into a write cycle (could
be I/O)
■ Non-cacheable data cache cycle into a write cycle (could be
I/O)
■ Cacheable data cache cycle into a write cycle (could be I/O)
■ Cacheable data cache cycle into a cacheable data cache
cycle
■ Cacheable data cache cycle into a non-cacheable data cache
cycle
■ Non-cacheable data cache cycle into a non-cacheable data
cache cycle
■ Non-cacheable data cache cycle into a cacheable data cache
cycle
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