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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

Figure 9. HOLD/HLDA Cycle

HLDA is negated one clock after HOLD is negated. Hold is not

recognized during locked cycles, but is recognized during

BOFF. An external master must monitor BOFF as well as

HLDA to determine bus ownership.

Bus Error Support

using PCHK and

APCHK

PCHK and APCHK are used for checking data parity and

address parity. Data parity is driven into the processor on pins

DP7–DP0 during reads, and is driven out of the same pins dur-

ing writes. The processor indicates a data parity error by

asserting PCHK two clocks after the validation of parity by

BRDY.

The AP signal provides even parity for the address bus. The

processor indicates an inquire parity error by asserting

APCHK two clock cycles after the address is validated by

EADS.

Special Bus Cycles Several bus cycles are supported by the AMD-K5 processor, as

illustrated in Table 6 on page 27. The byte enables are

encoded to define the type of cycle. Figure 39 on page 79 is a

timing diagram of a generic special bus cycle.

Flush Operations The FLUSH input is used by external logic to cause the proces-

sor to write back any modified lines in the data cache, and to

invalidate all entries in both the data cache and the instruction

cache. A special cycle is executed by the processor to indicate

completion of the FLUSH operation. The FLUSH input is

treated as a high-priority asynchronous interrupt, and is

acknowledged only on instruction boundaries.

CLK

ADS

BRDY

HLDA

HOLD

Data

Add/

Control

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AMD K5 Bedienungsanleitung Seite 54