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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

10.3 50-MHz Bus Operation

Table 21. CLK Switching Characteristics for 50-MHz Bus Operation

Symbol Parameter Description

Advance Info

Figure Comments

Min Max

Frequency 25 MHz 50 MHz

CLK Period 20.0 ns 40.0 ns 16

CLK Period Stability ± 250 ps Note 1

CLK High Time 4.0 ns 16 @ 2.0 V, Note 1

CLK Low Time 4.0 ns 16 @ 0.8 V, Note 1

CLK Fall Time 0.15 ns 1.5 ns 16 2.0–0.8 V, Note 1

CLK Rise Time 0.15 ns 1.5 ns 16 0.8–2.0 V, Note 1

Notes:

1. Not 100% tested; determined by design characterization.

Table 22. Delay Timing for 50-MHz Bus Operation

Symbol Parameter Description

Advance Info

Figure Comments

Min Max

ADSC, BE7–BE0, D/C, PWT, PCD, W/R, CACHE,

SCYC Valid Delay

1.0 ns 7.0 ns 17

AP Valid Delay 1.0 ns 8.5 ns 17

A31–A3, LOCK Valid Delay 1.1 ns 7.0 ns 17

ADS, M/IO Valid Delay 1.0 ns 7.0 ns 17

ADS, ADSC, AP, A31–A3, BE7–BE0, CACHE, D/C,

LOCK

, M/IO, PCD, PWT, SCYC, W/R Float Delay

10.0 ns 19

APCHK, IERR, FERR Valid Delay 1.0 ns 8.3 ns 17

PCHK Valid Delay 1.0 ns 8.3 ns 17

BREQ, HLDA Valid Delay 1.0 ns 8.0 ns 17

SMIACT Valid Delay 1.0 ns 8.0 ns 17

10a

HIT Valid Delay 1.0 ns 8.0 ns 17

10b

HITM Valid Delay 1.1 ns 6.0 ns 17

PRDY Valid Delay 1.0 ns 8.0 ns 17

D63–D0, DP7–DP0 Write Data Valid Delay 1.3 ns 8.5 ns 17

D63–D0, DP7–DP0 Write Data Float Delay 10.0 ns 19

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 99 100

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