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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

D63–D0 Data Lines Input/Output

The D63–D0 signals are the 64-bit data bus. These signals are

driven during the second and subsequent clocks of write

cycles, with valid bytes indicated by BE7–BE0. They are sam-

pled when the BRDY signal is asserted for read cycles. (See

Switching Characteristics t

and t

DP7–DP0 Data Parity Input/Output

The DP7–DP0 signals provide even parity, one for each of the

eight bytes of the data bus. The eight data parity signals corre-

spond to the eight bytes of the data bus as follows:

These signals are driven with the data bus. Read cycles that do

not provide even parity when the read data is driven result in

the assertion of PCHK. Byte enables are negated for invalid

data bytes. For systems that do not use parity, DP7–DP0 should

be connected to V

through a pull-up resistor. (See PCHK and

Switching Characteristics t

and t

EADS Valid External Address Input

The EADS signal indicates that a valid address is driven on the

address bus during inquire cycles. EADS has an internal pull-

up resistor. (See Switching Characteristics t

16a

and t

EWBE External Write Buffer Empty Input

External system logic notifies the processor of pending buff-

ered write cycles by negating the EWBE signal. The processor

will hold writes to exclusive or modified cache lines until

EWBE is asserted.

FERR Floating-Point Error Output

The FERR signal is asserted as a result of an unmasked float-

ing-point error. It is only floated during test.

■ DP7: D63–D56 ■ DP3: D31–D24

■ DP6: D55–D48 ■ DP2: D23–D16

■ DP5: D47–D40 ■ DP1: D15–D8

■ DP4: D39–D32 ■ DP0: D7–D0

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AMD K5 Bedienungsanleitung Seite 28