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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

HOLD Bus Hold Request Input

The HOLD signal is used to request the processor bus. When

this signal is asserted, the processor will complete all pending

bus cycles, float the bus, and assert the HLDA signal. This sig-

nal is not recognized during locked cycles. (See Switching

Characteristics t

and t

25b

IERR Internal Error Output

IERR indicates internal parity errors and functional redun-

dancy errors. Internal parity errors will cause IERR to be

asserted for one clock, and the processor will halt. Functional

redundancy errors, when configured as a Checker, will cause

IERR to be asserted in the second clock after the mismatched

output value was detected.

IGNNE Ignore Numeric Error Input

The IGNNE signal is used in conjunction with the NE bit in

CR0 to control response to numeric errors in the floating-point

unit. Numeric errors are handled internally when the NE bit is

set. When the NE bit is not set, errors are reported if IGNNE is

asserted and ignored when negated. (See Switching Character-

istics t

and t

INIT Initialize Input

The processor will perform a warm initialization when the INIT

signal is asserted. The INIT signal is similar to the RESET sig-

nal except that the data buffers, data cache, floating-point reg-

isters, instruction cache, and SMBASE registers are not

modified. The processor will perform a self-test if the INIT sig-

nal is sampled High at the falling edge of RESET.

INTR Maskable Interrupt Input

The INTR signal is used to generate interrupts. The interrupt

number is transferred to the processor during the interrupt

acknowledge cycle. To ensure that interrupts are acknowl-

edged, the INTR signal must be asserted until a locked inter-

rupt acknowledge cycle is complete. The INTR can be masked

by clearing the IF bit in the EFLAGS register. (See Switching

Characteristics t

and t

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AMD K5 Bedienungsanleitung Seite 30